Design Space Exploration for Dynamically Reconfigurable Multicore

Dynamical reconfigurable multicore processors, such as the E2 architecture, offer the ability to merge simple cores into larger ones in order to increase performance. However, the problem of deciding how to aggregate these cores is non-trivial and is highly dependent on the application. In this project, we investigate the problem of mapping multi-threaded applications written in a data-flow language to this type of architecture.

Supported by

Microsoft Research